1. Field of the Invention
The present invention relates to an active matrix substrate plate used in liquid crystal display apparatuses and a manufacturing method therefor, and relates in particular to an active matrix substrate plate having superior properties made by a manufacturing process based on simplified processing steps and improved yield.
2. Description of the Related Art
Active matrix type liquid crystal display apparatus using thin film transistors (abbreviated as TFT hereinbelow) as switching elements is constructed by placing a color filter substrate plate opposite to an active matrix substrate plate, in which independent pixel regions containing a TFT and a pixel electrode in each pixel region are arranged in a matrix, with an intervening liquid crystal layer. Also, a light blocking layer is provided on the color filter substrate plate or on the active matrix substrate plate in the TFT section and the boundary region in each pixel region.
An example of the circuit arrangement of the active matrix substrate plate is shown in FIG. 182. In FIG. 182, this active matrix substrate plate is formed such that a plurality of scanning lines 1011 are formed on a transparent insulation substrate plate and a plurality of parallel signal lines 1031 are formed on the transparent insulating substrate plate so as to cross the scanning lines at right angles across the gate insulation layer (not shown), and near the intersection of the scanning line and the signal line, an inverted staggered structure TFT 1060 comprised by a gate electrode 1012, an island-shaped semiconductor layer opposing the gate electrode across the gate insulation layer, and a pair of drain electrodes 1032 and source electrodes 1033 separated by a channel gap above the semiconductor layer. And in a window section Wd surrounded by a scanning line 1011 and a signal line 1031, there are provided a pixel electrode 1041 and an accumulation capacitance section 1070, in such a way that the gate electrode 1012 is connected to the scanning line 1011, the drain electrode 1032 to the signal line 1031, and the source electrode 1033 to the pixel electrode 1041.
The window section Wd and the scanning line 1011 and the signal line 1031 surrounding the window section, the region comprised by TFT 1060 are referred to as the “pixel region Px,” hereinbelow. A plurality of such pixel regions Px are arranged next to each other in a matrix pattern to construct a display surface Dp of the liquid crystal display apparatus.
The scanning lines 1011 are extended outside of the display surface Dp, and at the start end located at its tip, the scanning line terminal 1015 exposed on the surface of the active matrix substrate plate is formed. Also, each signal line 1031 is extended outside of the display surface Dp, and at the start end located at its tip, the signal line terminal 1035 exposed on the surface of the active matrix substrate plate is formed.
On the outside of the display surface Dp, a protective transistor 1080 may sometimes be attached for protecting the TFT connected to each signal line and scanning line, in case of excess current flow. And, the adjacent signal lines 1031, for the purpose of dispersing unexpected electrical shock and protecting the TFT in the pixel region, may sometimes be connected electrically to each other at the outside of the display surface Dp with a high resistance line.
On the outer peripheral section of the display surface Dp, for the purpose of preventing difficulties such as shorting between layers caused unexpected electrical shock generated on the active matrix substrate plate during the production by dispersing over all the wiring, or for the purpose of inspecting circuit defects, there are provided various kinds of peripheral circuits such as a gate-shut bus line 1091 for linking each scanning line 1011, a drain-shunt bus line 1092 for linking each signal line 1031, a connection section for connecting the gate-shunt bus line and the drain-shut bus line, inspection pads 1094 and 1095 for scanning lines and signal lines, respectively, and when manufacturing is completed, the peripheral circuits excepting the inspection pads are removed along with the substrate plate edge pieces.
The active matrix substrate plate having its edge pieces cutoff excepting the inspection pads is processed in such a way that respective scanning line terminals 1015 are connected to a not-shown scanning line driver, and the signal line terminals 1035 are connected to a not-shown signal line driver, and according to signals from respective drivers, specific individual pixel signals are input into the pixel electrode 1041 through each TFT 1060 in the pixel region.
The pixel electrode 1041 is disposed opposite to a common electrode 1014, and the liquid crystal in the pixel region is driven by applying a potential difference between the electrodes. There are two types of arrangement of the pixel electrode and the common electrode. In one type of configuration, as shown in FIG. 183A, the pixel electrode 1041 formed on the active matrix substrate plate and the common electrode 1014 formed over the entire display region of the color filter substrate plate are placed opposite to each other across the liquid crystal Lc, and this configuration is commonly called “twisted nematic type (referred to TN-type hereinbelow)”. The other configuration is, as shown in FIG. 183B, pixel electrode 1041 formed in a comb-teeth shape and the common electrode 1014 formed in a comb-teeth shape on the active matrix substrate plate are placed opposite to each other non-contactingly. This configuration is commonly called “in plane switching method” (referred to as the IPS type hereinbelow).
TFT 1060 has a gate electrode 1012 extending from the scanning line 1011 in each pixel region Px, an electrode (it is referred to as the drain electrode in the following) 1032 extending from the signal line 1031, an electrode (it is referred to as the source electrode, in the following) 1033 connected to the pixel electrode 1041, and when a scanning line signal is transmitted to the gate electrode 1012, drain electrode 1032 and source electrode 1033 selectively become conductive so that a pixel signal forwarded from the signal line 1031 is transmitted to the pixel electrode 1041, and the liquid crystal is driven by the potential difference generated between the pixel electrode 1041 and the common electrode 1014.
The accumulation capacitance section 1070 is comprised by an accumulation capacitance electrode 1071 and a common accumulation electrode 1072, and is provided for the purpose of holding the liquid crystal driving potential until the next selection signal is applied on the gate electrode 1012 by preventing, when the scanning line 1011 becomes non-selective, fluctuations in the potential caused by leaking of the liquid crystal driving potential applied on the pixel electrode 1041 through the TFT 1060 and the like. FIG. 182 shows a gate-storage type of capacitance accumulation in which the common accumulation electrode 1072 is connected to the forestage scanning line, but a common-storage type of capacitance accumulation in which the common accumulation electrode 1072 is connected to the common wiring 1013 may sometimes be used.
An example (for example, a Japanese Unpublished Patent Application, First Publication, Hei 9-120083) of manufacturing steps of active matrix substrate plate for a conventional TN-type liquid crystal display apparatus having the circuit configuration described above will be explained with reference to FIGS. 184A-184E. In this case, a combination of patterning and etching steps (referred to simply as etching hereinbelow) based on film deposition and photolithography technique is regarded as one processing step. Also, in the following explanations, the location where the pixel region 1041 of the active matrix substrate plate is formed will be referred to as the window Wd, the location where TFT 1060 is formed as the TFT section Tf, the location where the accumulation capacitance section 1071 is formed as the accumulation capacitance section Cp, and outer peripheral regions of the display surface Dp where peripheral circuits such as terminals are formed as the outer peripheral section Ss.    (Step 1) As shown in FIG. 184A, a metallic layer 1010 is formed on the glass plate 1001, and excepting the scanning line 1011 (not shown) and the gate electrode 1012 extending from the scanning line to the TFT section Tf, the scanning terminal 1015 extending to the outer periphery section Ss, and the common accumulation electrode 1072 of the accumulation capacitance section Cp, the metallic layer 1010 is removed by etching.    (Step 2) As shown in FIG. 184B, laminating successively the gate insulation layer 1002 and the semiconductor layer 1020, comprised by an amorphous silicon layer 1021 and an n+ amorphous silicon layer 1022, on the transparent insulation substrate plate, the semiconductor layer 1020 is removed excepting the TFT section Tf.    (Step 3) As shown in FIG. 184C, a metallic layer 1030 is formed on the transparent insulation substrate plate, and excepting the signal line 1031, signal line terminal 1035 extending from the signal line to the outer peripheral section Ss, drain electrode 1032, and source electrode 1033, the metallic layer 1030 is removed by etching. Next, using the remaining metallic layer as masking, the n+ amorphous silicon layer 1022 exposed at the channel gap 1023 in the TFT section is removed.    (Step 4) As shown in FIG. 184D, a protective insulation layer 1003 is formed on the transparent insulation substrate plate, and a first opening 1061 reaching the signal line terminal 1035 by punching through the protective insulation layer 1003 in the outer peripheral section Ss, a second opening 1062 reaching the source electrode 1033 by punching through the protective insulation layer 1003 in the TFT section Tf, and a third opening 1063 reaching the scanning line terminal 1015 by punching through the protective insulation layer 1003 and the gate insulation layer 1002 in the outer peripheral section Ss are formed by etching.    (Step 5) As shown in FIG. 184E, a transparent conductive layer 1040 is formed on the transparent insulation substrate plate, and excepting the pixel electrode 1041 extending to the window section Wd and connected to the source electrode 1033 through the second opening 1062 in the TFT section Tf, the accumulation capacitance electrode 1071 extending from the pixel electrode above the common accumulation electrode 1072 in the accumulation capacitance section Cp, the terminal pad 1095 exposed above the signal line terminal 1035 through the first opening 1061 and above the scanning line terminal 1015 through the third opening 1063 in the outer peripheral section Ss, the transparent conductive layer 1040 is removed by etching to complete the processing steps.
Although there have been many methods other than the process described above for manufacturing the active matrix substrate plates, when a combination of film depositing, patterning and etching processes is regarded as one processing step, all the conventional methods require five processing steps or more. However, in recent years, in place of cathode ray tubes as a display device for personal computers and monitors, liquid crystal display apparatuses are beginning to be used frequently, and along with this trend, there has been strong demand for lowering the cost of large liquid crystal display screens. Lowering the cost of liquid crystal display apparatus requires an integrated effort to lower the cost, but one element of such effort is simplification of the manufacturing process. Especially, if the photolithographic steps are increased, resulting higher number of processing steps leads to the necessity for large investments in facilities while increasing the probability of yield drop, methods of reducing the number of etching steps have been sought actively.
Further, according to the conventional manufacturing methods, to form peripheral circuits such as protective transistors, even more processing steps are sometimes required, and drop in yield caused by etching operation has also been experienced, which is caused by infiltration corrosion of needed underlying layers which should have been left intact.
Various methods for reducing the number of etching have been proposed in the past. For example, according to a Japanese Patent No. 2570255, Second Publication, and a Japanese Unpublished Patent Application, First Publication, Showa 63-15472, in step 1, scanning line and gate electrode are formed, in step 2, after forming films for gate insulation layer and semiconductor layer and metallic layer, excepting the regions where signal line and drain electrode and source electrode are continued, the metallic layer and the semiconductor layer are removed by etching, in step 3, after forming the transparent conductive layer, the transparent conductive layer and channel gap metallic layer are removed by etching except the signal line, the drain electrode, source electrode and pixel electrode extending from the source electrode, and next, removing the n+ amorphous silicon layer using the remaining transparent conductive layer as masking, and in step 4, after forming a protective insulation layer, the protective insulation layer on the pixel electrode is removed by etching, thus constituting a process comprised by four steps. However, according to this method, because the gate metallic layer and drain metallic layer are not electrically convertible, protective transistors cannot be formed, so that the yield has been a problem.
Also, a Japanese Unpublished Patent Application, First Publication, Hei 7-175084 discloses a process in which, in step 1, scanning line and gate electrode are formed, in step 2, after forming films of gate insulation layer and semiconductor layer, excepting the semiconductor layer of the TFT section, a gate insulation layer and semiconductor layer are removed by etching in step 3, after forming the transparent conductive layer, excepting the signal line, pixel electrode, drain electrode and source electrode, the transparent conductive layer is removed next, using the remaining transparent conductive layer as masking, n+ amorphous silicon layer is removed, and in step 4, after forming a protective insulation layer, the protective insulation layer above the pixel electrode is removed, thus constituting a process comprised by four steps. However, this method has a problem of quality of displays and the yield, because the signal lines, drain electrodes, source electrodes and others are made only of transparent conductive layer (ITO, indium tin oxide) that has high resistance and susceptible to causing film defects.
Further, a Japanese Unpublished Patent Application, First Publication, Hei 8-146462, proposes, in step 1, to form scanning line and gate electrode and in step 2, after forming films of the gate insulation layer, the semiconductor layer and metallic silicide layer, excepting the portions linking the signal line, drain electrode and source electrode, the metallic silicide layer, semiconductor layer, and gate insulation layer are removed by etching and in step 3, after forming films of the transparent conductive layer and metallic layer, excepting the signal line, drain electrode, source electrode and the pixel electrode linking the signal line, drain electrode and source electrode and pixel electrode linked to the source electrode, the metallic layer and the transparent conductive layer are removed by etching and next, using the remaining metallic layer as masking, removing the n+ amorphous silicon layer, and in step 4, after forming a protective insulation layer, the protective insulation layer above the pixel electrodes and the metallic layer are removed by etching, thereby constituting a 4-step process.
However, the methods according to a Japanese Unpublished Patent Application, First Publication, Hei 7-175084 and a Japanese Unpublished Patent Application, First Publication, Hei 8-146462, during etching of the metallic layer of signal lines and transparent conductive layer or protective insulation layer, due to infiltration of etching solution, signal line may be severed or the scanning lines in the lower layer and circuit elements of the gate electrodes and the like may become corroded and/or scanning line and signal line may become shorted, which cause poor yield or problems in the properties of the active matrix substrate plate, and therefore, it was difficult to put these techniques into practice.